Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - AMBA 3.0

Search list

[Other] amba3core

Description: amba3 sva 完全验证的代码，有verilog的和systemverilog的-amba3 sva fully validate the code, and the Verilog and SystemVerilog
Platform: | Size: 280576 | Author: kevin | Hits:

[ARM-PowerPC-ColdFire-MIPS] AMBA

Description: SystemC写的AMBA 3.0 AXI总线事物级TLM模型 正在调试。有详细实验报告说明。-AMBA 3.0 AXI TLM SystemsC
Platform: | Size: 4893696 | Author: zhouli | Hits:

[VHDL-FPGA-Verilog] handshake

Description: AMBA 3 AXI handshake protocol. Verilog platform. master and slave.
Platform: | Size: 196608 | Author: nodeity | Hits:

[VHDL-FPGA-Verilog] AN123

Description: AMBA Application Note: AN123 - Logic Tile IT1 GPIO example design. -Application note AN123 provides all of the AHB slave features of AN119 with the addition of five 32bit AHB GPIO slaves. The GPIO interfaces are used to configure and test an IT1 board. The following board combinations are supported: Core Module+ Integrator/IM-LT1+ LT-XC2V6000+ IT1 Core Module+ Integrator/IM-LT1+ LT-XC2V8000+ IT1 Integrator/CP+ Core Module+ Integrator/IM-LT1+ LT-XC2V6000+ IT1 Integrator/CP+ Core Module+ Integrator/IM-LT1+ LT-XC2V8000+ IT1 PB926EJ-S+ LT-XC2V6000+ IT1 PB926EJ-S+ LT-XC2V8000+ IT1 Asynchronous and Synchronous bridge modes are supported on the PB926EJ-S with different design images. Asynchronous mode is selected using SW1[3] on the PB926EJ-S.
Platform: | Size: 4482048 | Author: 余曉民 | Hits:

[VHDL-FPGA-Verilog] Axi_mux

Description: The elements come from the necessity of creating generic modules, in the verification phase, for this widely used protocol. These primitives are presented as a not compiled library written in SystemC where interfaces are the core of the library. The definition of interfaces instead of generic modules let the user construct custom modules improving the resources spent during the verification phase as well as easily adapting his own modules to the AMBA 3 AXI protocol. As validation scenario, results obtained for an AXI bus connecting IDCT and other processing resources for MPEG4 video decoding are presented.
Platform: | Size: 41984 | Author: Paul Stephen | Hits:

[Driver Develop] arm-gcc-3.4.4-gm8180.tar.bz2

Description: GM’s GM8180 MDC1 hardware environment is a highly efficient RISC-based platform for the purpose of verifying and evaluating AMBA-based designs in the early development stage. The complete set of MDC1 GM8180 platform consists of a main board (MB120) equipped with GM8180 chip and an embedded GM FA626 CPU.-Hardware: Intel x86 compatible PC Standard 16550 UART Software: Standard Linux distribution (Fedora core 2.6.14-FC5 or above) FA626-based Linux distribution
Platform: | Size: 54044672 | Author: 北科 | Hits:

[Software Engineering] shruthi-proj

Description: The APB is part of the AMBA 3 protocol family. It provides a low-cost interface that is optimized for minimal power consumption and reduced interface complexity. The APB interfaces to any peripherals that are low-bandwidth and do not require the high performance of a pipelined bus interface. The APB has unpipelined protocol. All signal transitions are only related to the rising edge of the clock to enable the integration of APB peripherals easily into any design flow. Every transfer takes at least two cycles. The APB can interface with the AMBA Advanced High-performance Bus Lite (AHB-Lite) and AMBA Advanced Extensible Interface (AXI). You can use it to provide access to the programmable control registers of peripheral devices.-The APB is part of the AMBA 3 protocol family. It provides a low-cost interface that is optimized for minimal power consumption and reduced interface complexity. The APB interfaces to any peripherals that are low-bandwidth and do not require the high performance of a pipelined bus interface. The APB has unpipelined protocol. All signal transitions are only related to the rising edge of the clock to enable the integration of APB peripherals easily into any design flow. Every transfer takes at least two cycles. The APB can interface with the AMBA Advanced High-performance Bus Lite (AHB-Lite) and AMBA Advanced Extensible Interface (AXI). You can use it to provide access to the programmable control registers of peripheral devices.
Platform: | Size: 250880 | Author: psn026 | Hits:

[VHDL-FPGA-Verilog] axi_ipif_v2.3

Description: The AXI4-Lite IP Interface (IPIF) is a part of the Xilinx family of Advanced RISC Machine (ARM) Advanced Microcontroller Bus Architecture (AMBA) Advanced eXtensible Interface (AXI) control interface compatible products. It provides a point-to-point bidirectional interface between a user Intellectual Property (IP) core and the AXI interconnect.
Platform: | Size: 403456 | Author: forestmeng | Hits:

[] AMBA 3 APB Protocol Specification.pdf

Description: AMBA 3 APB Specification
Platform: | Size: 189440 | Author: thekkk | Hits:

[] AMBA 3 AXI Protocol Specification.pdf

Description: AMBA 3 AXI Specification
Platform: | Size: 409600 | Author: thekkk | Hits:

[Program doc] xilinx ZYNQ开发板教程

Description: ZYNQ 是 Xilinx 推出的 FPGA 加 ARM 解决方案，片内总线采用 AXI 总线协议（AMBA 3.0）， 相比较于常用的 AHB 总线协议（AMBA 2.0），其性能和带宽均有大幅提升。随着数字系统越来 越复杂，软硬件协同设计越来越困难，FPGA 加 ARM 这种低成本 SoC 解决方案是大势所趋。 xilinx ZYNQ开发板教程
Platform: | Size: 35683815 | Author: zzwlion22 | Hits:

CodeBus www.codebus.net